Efficient minimization Techniques for Threshold Logic Gate
نویسندگان
چکیده
optimization techniques are discussed using digital logic network using threshold logic. Almost same energy consumption changing speedup is possible using threshold network and many complex functions can be implemented using threshold logic with lesser number of logic gate and logic level for which these optimization techniques becomes popular for digital system design and applications. In this article, we analysis different present optimization techniques of capacitive threshold-logic gate (CTLG), resonant tunneling diode (RTD), single electronics transistor based threshold gate (SET), Charge Recycling (CR) CMOS threshold logic gate and Memristor Threshold Logic and also analysis systematically among them.
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